The present invention relates to an integrated circuit and, more particularly, to a semiconductor device suitable for use in a large scale integration employed in, for example, a large-sized electronic computer, the semiconductor device comprising a substrate on which a multiplicity of circuit elements are formed, and power bus layers provided on the substrate for feeding power to the respective circuit elements.
In conventional integrated circuits employed in, for example, electronic computers, power buses such as those shown in FIG. 14 are generally used for feeding power to the respective gates which are integrated into the circuits. In FIG. 14A, the reference numeral 111 denotes an LSI chip, while 112 represents bonding pads, and 116 to 119 denote power buses for feeding power to respective gates. The power bus 116 is connected to power pads 113. The other power buses are also connected respective pads, but this is not essential to the present invention, and description and illustration thereof are therefore omitted.
FIG. 14B is an enlarged view of a region 11C which is surrounded by the circle in FIG. 14A.
The power bus 116 is connected to power buses 11A in another layer through through-holes 11B, and power is fed to gates 11D from the power buses 11A, respectively.
As a gate, an emitter coupled logic (hereinafter referred to as an "ECL") such as that shown in FIG. 15 is widely employed in a high-speed LSI used in, for example, an electronic computer. The negative voltage source V.sub.EE of the ECL is fed with power through, for example, the power buses 116 and 11A shown in FIG. 14B. In this case, the current path is formed as indicated by the arrows 11E. FIG. 16 shows the drop of voltage in the current path. The axis of the abscissa of the graph shown in FIG. 16 represents the gate position in a direction of X (a direction parallel with the power bus 116 shown in FIG. 14), and the axis of the ordinate represents the drop of voltage. The section 126 surrounded by the one-dot chain line represents one of the circuit groups. The numeral 116 expresses a bus for the negative voltage source V.sub.EE. The curves 121 to 123 show changes in the voltage drop occurring when the current supplied to each of the gates is increased.
LSIs generally have one or a plurality of bias circuits for the purpose of compensating for possible fluctuations in the supply voltage fed thereto. When it is necessary to compensate for possible variations in the supply voltage within the chip, each gate may have a bias circuit. However, if each gate is provided with a bias circuit, the layout square measure for each gate increases, and the power consumption also increases. One of the techniques to overcome this problem is an LSI arranging method which is mentioned in the specification of Japanese Patent Laid-Open No. 204624/1983. In this method, all of the gates are divided into a plurality of gate groups, and a bias circuit is provided for each gate group so as to compensate for possible variations in the supply voltage for a plurality of gates. Thus, the potential variations within each gate group are reduced as compared with the potential variations in the entire chip, so that this arrangement can be used within a range within which the degree of variations is so low that they can be ignored. However, as will be clear from the graph shown in FIG. 16, the supply voltage variations within each gate group 126 tend to increase, for example, as shown by the reference numeral 125, as the scale of integration of the LSI is enlarged or the circuit current is increased. To reduce such a drop of voltage, it is necessary to decrease the ratio of the number of gates in each gate group 126 to the number of bias circuits. This, however, involves the problem that the degree of integration of the LSI as a whole is lowered and the power consumption is increased.